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Embedded Systems Software Engineer | Systems & Kernel Specialist
About Me
I'm an embedded software engineer working on safety-critical, real-time systems. Most of my work focuses on Linux and Barebox OS bring-up and low-level I/O driver development, along with hardware-software co-design and optimizing memory pipelines under hard real-time scheduling constraints. I also write firmware for coprocessors, though that tends to sit alongside the driver and OS work rather than being the main thing.
This page is a small tribute to the old academic homepages. There's no telemetry here, no tracking cookies, and no bloated frameworks. Just clean text, some C code, and a few terminal-style controls.
Professional Background
Over the past 8+ years, I've built software and drivers across several safety-critical domains:
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Aerospace & Defense Systems:
- Linux & Barebox SoC Integration: Handled bootloader and OS bring-up for a custom Cortex-A75 SoC, taking the secure boot chain from BootROM through Barebox and into the Linux kernel.
- ARM Architecture Optimization: Wrote assembly and C-level optimizations for ARMv8-A pipelines, leaning on cache-aware layouts, lock-free queues, and AArch64 tuning to push data ingestion on high-throughput DMA engines.
- IRAD Rust Research: Ran an Internal Research and Design (IRAD) effort looking into Rust's memory-safety guarantees and compiler validation models for real-time safety-critical defense software.
- Training & Simulation Engineering: Wrote C software for flight weapons simulators, keeping low-latency, multi-threaded subsystems on VxWorks inside hard real-time execution bounds.
- Industrial Automation Systems: Built C++ backend components for distributed industrial control loop engines, managing cascade and PID scheduling deadlines.
My usual toolchain is GCC/Clang, Yocto, GDB/JTAG debuggers, and Vim. I mostly write C, C++, and ARM Assembly, with Rust for secondary utilities.
Research & Development Laboratory
Notes on HDL/FPGA hardware design, QEMU system emulation, and device modeling.
1. HDL & FPGA Core Prototyping
Co-designing software and custom hardware accelerators means modeling system buses and logical pipelines first. I use SystemVerilog and VHDL to prototype soft cores, register interfaces, and custom DMA logic on FPGA fabric. Pushing processing pipelines down into dedicated hardware logic gives you tight, predictable cycle bounds for the timing-critical loops.
2. QEMU Device Emulation & Virtual Prototyping
Building bootloaders like Barebox and low-level kernel drivers before the custom silicon is ready means you need cycle-accurate models to develop against. I write custom QEMU machine configurations and peripheral models in C to stand in for the real hardware.
Once the interrupt handlers (IRQs), DMA registers, and memory-mapped address tables are modeled in QEMU, the same driver code can be tested and verified inside automated virtual integration environments. That takes hardware availability off the critical path and lets you validate early architecture decisions before anything is taped out.
That same interest in full-system emulation is what drives the System Terminal playground below. Pressing BOOT RISC-V starts a genuine 64-bit RISC-V machine, CPU, MMU, and virtio block/network devices and all, running entirely in your browser as WebAssembly. The emulator core is TinyEMU, written by Fabrice Bellard (the original author of QEMU and FFmpeg). I pair it with a small Alpine Linux image I build and host myself, so you can boot real Linux and compile C right from the browser.
3. ARM Architecture-Specific Optimization
I have a soft spot for low-level performance tuning and architecture-specific optimization on modern ARM cores. A lot of that work centers on the ARMv8.2-A instruction set, using SIMD (Neon) vectors and the dot-product extensions to speed up compute-heavy math pipelines and DSP routines down at the bare-metal level.
System Terminal
A simulated shell, and a real RISC-V Linux machine, emulated in your browser.
The prompt below is a small simulated shell (type help to explore). Click
BOOT RISC-V and it becomes the real thing: Fabrice Bellard's TinyEMU
compiled to WebAssembly, booting a self-hosted 64-bit RISC-V Alpine Linux image off an
on-demand virtual disk. Write C, compile it with tcc, and run it, or
apk add more packages over the network. None of it is faked; it's a full CPU
emulator running an actual Linux kernel and userland. Emulator © Fabrice Bellard (MIT).