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Embedded Systems Software Engineer | Systems & Kernel Specialist
About Me
I am an embedded software engineer specializing in safety-critical, real-time systems. Most of my work involves hardware-software co-design, developing low-level device drivers, writing deterministic firmware for coprocessors, and optimizing memory pipelines under hard real-time scheduling constraints.
This page is a simple tribute to classic academic homepages. Here you will find no telemetry, tracking cookies, or bloated frameworks. Just clean text, basic C code, and simple terminal-style controls.
Professional Background
Over the past 8+ years, I have built software and drivers across several safety-critical domains:
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Aerospace & Defense Systems:
- Linux & Barebox SoC Integration: Developed bootloader and OS bring-up strategies for a custom Cortex-A75 SoC, managing the secure boot chain from BootROM through Barebox initialization and handoff to the Linux kernel.
- ARM Architecture Optimization: Engineered assembly and C-level ARCH optimizations targeting ARMv8-A pipelines, using cache-aware layouts, lock-free queues, and ARM Assembly (AArch64) tuning to optimize data ingestion on high-throughput DMA engines.
- IRAD Rust Research: Led Independent Research and Development (IRAD) investigating Rust's memory-safety guarantees and compiler validation models for real-time safety-critical defense software.
- Training & Simulation Engineering: Developed C software for flight weapons simulators, maintaining low-latency, multi-threaded subsystems on VxWorks under hard real-time execution bounds.
- Industrial Automation Systems: Constructed C++ backend components for distributed industrial control loop engines, managing cascade and PID scheduling deadlines.
My toolchain of choice includes GCC/Clang, Yocto, GDB/JTAG debuggers, and Vim. I primarily write in C, C++, and ARM Assembly, and write secondary utilities in Rust.
Research & Development Laboratory
Notes on HDL/FPGA hardware design, QEMU system emulation, and device modeling.
1. HDL & FPGA Core Prototyping
Co-designing software and custom hardware accelerators requires modeling system buses and logical pipelines. I use SystemVerilog and VHDL to prototype soft cores, register interfaces, and custom DMA logic implemented on FPGA fabric. Offloading processing pipelines to dedicated hardware logic provides deterministic cycle bounds for timing-critical loops.
2. QEMU Device Emulation & Virtual Prototyping
Developing bootloaders (such as Barebox) and low-level kernel drivers before custom silicon target designs are completed requires cycle-accurate modeling interfaces. I write custom QEMU machine configurations and peripheral model structures in C to support virtualization.
By modeling interrupt handlers (IRQs), DMA registers, and memory-mapped address tables in QEMU, the exact same driver code can be tested and verified inside automated virtual integration environments, mitigating hardware supply bottlenecks and validating early architecture layouts.
That same fascination with full-system emulation is what drives the System Terminal playground below. Pressing BOOT RISC-V starts a genuine 64-bit RISC-V machine — CPU, MMU, and virtio block/network devices — running entirely in your browser as WebAssembly. The emulator core is TinyEMU, written by Fabrice Bellard (the original author of QEMU and FFmpeg). I pair it with a small Alpine Linux image I build and host myself, so you can boot real Linux and compile C from the browser.
3. ARM Architecture-Specific Optimization
I have a strong personal interest in low-level performance tuning and architecture-specific optimization for modern ARM cores. My work frequently focuses on exploiting the ARMv8.2-A instruction set architecture, specifically utilizing advanced SIMD (Neon) vectors and specialized dot-product extensions to accelerate compute-heavy mathematical pipelines and digital signal processing routines directly at the bare-metal level.
System Terminal
A simulated shell — and a real RISC-V Linux machine, emulated in your browser.
The prompt below is a small simulated shell (type help to explore). Click
BOOT RISC-V and it becomes the real thing: Fabrice Bellard's TinyEMU
compiled to WebAssembly, booting a self-hosted 64-bit RISC-V Alpine Linux image off an
on-demand virtual disk. Write C, compile it with tcc, and run it — or
apk add more packages over the network. Nothing is faked; it is a full CPU
emulator running an actual Linux kernel and userland. Emulator © Fabrice Bellard (MIT).